A circuit illustrated in FIG. 6, by way of example, is known as a typical circuit for outputting an input signal upon reducing the signal waveform width (namely the time, also sometimes referred to as “pulse width”, from either a positive-going transition or a negative-going transition of the signal to the negative-going or positive-going transition that occurs following the first-mentioned transition. In a CMOS inverter array (INV11 to INV16) shown in FIG. 6, the value of the ratio between an NMOS transistor and a PMOS transistor (the gain-coefficient ratio βn/βp of each of the MOS transistors) is changed alternatingly at CMOS inverters in front and back (βn/βp=⅛ in the case of INV11, INV13, INV15 and βn/βp= 2/4 in the case of INV12, INV14, INV16), and the transfer speed of a positive-going transition from LOW to HIGH of a signal at an input terminal and the transfer speed of a negative-going transition from HIGH to LOW are made to differ from each other. As a result, the positive-going transition from LOW to HIGH of a signal that is output from a terminal 2 is slowed in accordance with the positive-going transition from LOW to HIGH at terminal 1, and the negative-going transition from HIGH to LOW of a signal that is output from the terminal 2 is hastened in accordance with the negative-going transition from HIGH to LOW at terminal 1. The width of the waveform is reduced by an amount equivalent to the difference between the two delays.
Further, in a circuit illustrated in FIG. 7, a signal from an input terminal 1 is supplied as is to one input of a two-input AND gate 13 and is supplied to a second input of the AND gate 13 via a delay circuit 14. In a case where the signal at input terminal 1 undergoes a LOW-to-HIGH positive-going transition, output terminal 2 does not undergo a change to the HIGH level until the two inputs of AND gate 13 both go HIGH. That is, the positive-going transition at output terminal 2 is delayed by an amount equivalent to the delay of the delay circuit 14 from the timing of the LOW-to-HIGH positive-going transition of the signal at input terminal 1. In a case where the signal at input terminal 1 undergoes a HIGH-to-LOW negative-going transition, the output terminal 2 is placed at the LOW level if either one of the two inputs of AND gate 13 goes LOW. The signal at output terminal 2 therefore falls from HIGH to LOW without any delay from the delay circuit 14. Consequently, the signal waveform at output terminal 2 has its width reduced by an amount equivalent to the difference between the times of the HIGH-to-LOW and LOW-to-HIGH transitions.
The configurations illustrated in FIGS. 6 and 7 always reduce the width of a signal waveform irrespective of the width of the waveform. Consequently, in a case where the width of an input signal waveform is not large enough with respect to the shortened width, the output waveform width is reduced too much and made too narrow. As a result, a problem arises in a circuit (not shown) downstream of the waveform-width adjusting circuit or the maximum amplitude fails to exceed a threshold value in a binary pulse waveform. There is a possibility that the waveform itself may vanish.